The present invention relates to data communication and more particularly to high speed communication links.
As is well known, data transport between devices may include separated data and clock streams or a clock stream may even be encoded in the data stream. Each approach includes significant limitations. For example, having separate clock and data lines requires additional power, space and logic to support the communication link. Additionally, stable high speed communication on separate clock and data lines requires that the lines be accurately matched in length, size, etc. The use of separate clock and data paths will continue to be limited as processing speed continues to increase.
The issue of separate delay paths is eliminated when the clock signal is encoded within the data signal. However, an encoded signal may significantly increase the required transfer speed necessary to maintain device performance. For a given signaling speed the information transfer rate of a data signal encoded with a clock signal is lower than the data transfer rate would be along a separated data line. Similarly, at a fixed data transfer rate a data signal encoded with a clock signal would require faster processing speed as compare to a separated data line. Simply increasing the signaling speed may not be a viable option as faster processing may increase in power consumption, expense, etc.
With the ever increasing density of digital electronics, it would desirable to be able to reduce the number of signal lines while avoiding the limitations of encoded data streams.